AI PCB Design: How AI Actually Designs a Circuit Board

Ask ten hardware engineers whether a machine can lay out a board and you get ten answers, most of them wrong in one direction or the other. AI PCB design is neither a parlor trick nor vapourware. It is a chain of specific, individually solvable steps, several with deterministic algorithms thirty years old, now stitched together and driven by a model that reads intent from a sentence like "a USB-C powered ESP32 sensor node with two relay outputs". This article walks that pipeline honestly: what happens at each stage, where the failure modes hide, and which parts still belong to a person.

What "AI PCB design" actually means

When people search for artificial intelligence PCB tools, they usually mean one of three quite different things:

• Assistive AI inside a CAD tool — net-name autocomplete, a chatbot that explains a datasheet, a plugin that suggests decoupling. Useful, but you still do the work.
• Generative layout on an existing schematic — you supply the netlist, the tool places and routes it. Most published academic work sits here.
• End-to-end synthesis — a plain-language requirement goes in; parts, schematic, layout, checks and factory files come out.

The third is what most people picture, and the one worth explaining, because it is also where a plausible-looking output can be quietly worthless. A board that renders beautifully in 3D and cannot be assembled is not a design; it is a picture.

The pipeline: how AI circuit board design works, step by step

1. Requirements to architecture

The first job is turning ambiguous English into an electrical block diagram: supply rails and their currents, the main IC, level shifting, protection, connectors, indicators. This is where a language model earns its place. It has read an enormous number of datasheets and reference designs, so it knows a 5 V relay coil needs a transistor and a flyback diode rather than a GPIO, and that a USB-C sink needs 5.1 kΩ CC pull-downs. It is also where a model can confidently invent a topology that never worked, so good implementations pin this stage to known-good building blocks.

2. Part selection against real stock

The architecture is resolved into orderable parts. This step matters more than beginners expect, and has its own section below.

3. Schematic and netlist

The schematic humans look at is a drawing; the artifact the rest of the pipeline consumes is the netlist, a list of which pins are electrically joined. Placement, routing and DRC are all transformations of that connectivity. A tool that produces a pretty schematic image but no consistent netlist has produced nothing usable, which is why serious implementations drive a real EDA kernel such as KiCad and treat the netlist as the source of truth.

4. Electrical rule check (ERC)

ERC is cheap and catches embarrassing mistakes: pins connected to nothing, two outputs driving the same net, power inputs with no source, single-pin nets that were meant to join something. It does not know whether your circuit works, only whether the graph is self-consistent.

5. Footprints

Each symbol gets a physical land pattern: pad sizes and positions, courtyard, silkscreen, 3D anchor. This is where machine-generated boards most often die quietly, because the mistakes are invisible on screen. SOT-23-3 versus SOT-23-5. SOIC-8 versus MSOP-8. Imperial 0603 versus metric 0603, which differ by nearly a factor of two in length. Pin 1 rotated 90° on a QFN. The only reliable defense is binding each footprint to the exact manufacturer part number, never a generic package name.

6. Placement

Placement decides most of a board's electrical behavior before a single track is drawn, and its heuristics are encodable: decoupling capacitors within a few millimeters of their supply pin, crystals hugging the MCU with a small loop area, connectors on the edge facing outward, a switching regulator's hot loop kept physically tiny, heat sources away from temperature sensors, keep-out under an antenna. A machine applies all of them consistently, which is more than can be said for a tired human at 1 a.m.

7. Routing and copper pours

Netlist plus placement becomes copper, then a ground pour is added and stitched with vias so return currents have somewhere sensible to go. Autorouting is covered below.

8. Design rule check (DRC)

DRC compares the geometry against the fabricator's capabilities and against itself: copper-to-copper clearance, annular ring, drill-to-copper, silkscreen over pads, courtyard overlaps, tracks crossing the board outline and, critically, unrouted nets. One unconnected net is a dead board.

9. 3D model and factory files

The last step exports what a factory can read: Gerbers for each copper, mask and silkscreen layer, an Excellon drill file, a bill of materials, and a pick-and-place (CPL) file giving each part's position and rotation. The 3D model is not decoration; it is the cheapest way to catch a connector facing into the board. Our guide to PCB manufacturing files breaks each format down.

BuildPCB implements exactly this chain from a plain-language brief: catalog lookup, schematic, ERC, footprint assignment, placement, autoroute, pour, DRC, 3D model, then Gerbers, drill files, BOM and CPL that any manufacturer accepts.

Why real-stock part selection decides everything

A schematic full of unbuyable components is worthless, and this is what separates a demo from a tool. A general-purpose model asked for a buck converter will happily name a part discontinued in 2019, one with a 26-week lead time, or one your factory cannot fit.

The fix is not cleverer prompting, it is grounding: selection must happen inside a live catalog with real stock levels, prices, package data and manufacturer part numbers. BuildPCB selects from more than 780,000 in-stock JLCPCB/LCSC components, so the BOM it emits can be quoted and assembled rather than admired. It also constrains the design usefully: if no 0.5 Ω sense resistor is in stock, you get one that is.

• Prefer common parts. Assembly houses charge a setup fee for anything outside their standing library, which can outweigh the PCB cost on a five-board run.
• Check the package, not just the chip. The same IC in QFN and TSSOP can differ wildly in availability.
• Watch rotation conventions. Diodes, LEDs and electrolytics fitted backwards usually trace to a CPL rotation mismatch, not a layout error.

What autorouting can and cannot do

Autorouting is old technology, and its limits are the fastest way to calibrate your expectations of any AI PCB design software. An autorouter solves a geometry problem: connect these pin pairs on N layers without violating clearance. Modern routers do it well on two- and four-layer boards of moderate density, and the result passes DRC.

What no autorouter models:

• Return current. It routes the signal, not the loop. A trace hopping layers over a plane split creates a return detour the router cannot see.
• Controlled impedance. Track width for a 50 Ω single-ended or 90 Ω differential line depends on your stackup's dielectric height. Unless someone computed it and set a rule, you get the default width.
• Current capacity and heat. Nothing in the algorithm objects to a 0.2 mm trace carrying 3 A.
• Sensitive analog. Kelvin connections, guard rings and star grounds exist only if expressed as constraints.

Traditional CAD versus an AI-assisted workflow

Where AI PCB design still needs a human

• High-speed digital. DDR, USB 3.x, HDMI, gigabit Ethernet: anything where edge rates make the interconnect a transmission line. Length matching, skew budgets, reference-plane continuity and a defined stackup are inputs, not afterthoughts.
• RF. Matching networks, keep-outs, ground reference under the feed line, and the fact that a 50 Ω trace is only 50 Ω on one stackup. Antennas need tuning on real hardware.
• Power and thermal. Converter loop inductance, copper area as a heatsink, input capacitor ripple ratings, derating at temperature. Real physics, real arithmetic.
• Safety and isolation. Anything touching mains. Creepage and clearance distances, isolation barriers, fusing and standards such as IEC 62368-1 are legal requirements.
• Certification. FCC Part 15, CE/UKCA, EMC pre-compliance. No tool passes these for you, and layout choices made months earlier decide whether you will.

When not to use AI for a board

1. It connects to mains, a person, or a vehicle. Medical, automotive and industrial safety work needs a qualified engineer and a documented process.
2. You cannot evaluate the output. If you could not tell a correct schematic from a subtly wrong one, speed only gets you to a broken board faster. Start with our beginner's guide to PCB design software and the how to make a PCB walkthrough instead.
3. The board is dense HDI or large BGA. Fine-pitch escape routing, via-in-pad and buried vias are still specialist manual work.
4. Unit cost dominates. At 50,000 units, an engineer who removes a layer or ten cents of BOM pays for themselves many times over.
5. A proven design already exists. A board that has passed EMC beats a fresh one, however elegant.

Using it responsibly

1. Write a specific brief. "IoT board" produces guesswork; "5 V USB-C in, 3.3 V at 500 mA, ESP32-C3, two 5 V relay outputs, 50 × 50 mm" produces a design. We cover this in how to describe a PCB to an AI.
2. Read the schematic before the layout. Almost every serious error is visible there: rails, pull-ups, decoupling, protection, ratings.
3. Check the BOM line by line for voltage rating, tolerance, package and stock.
4. Open the fab files in a Gerber viewer. Thirty seconds catches missing pours, silkscreen over pads and wrong drills.
5. Order a prototype before you order a hundred. Five boards cost less than lunch and tell you the truth.

The honest summary: AI has compressed the mechanical parts of board design — catalog search, symbol drawing, footprint hunting, placement, routing, export — from days into minutes, and left the judgement where it was. That is still a large win, especially for a first prototype that would otherwise never be built. The manual covers the web studio and macOS app, and pricing is pay-as-you-go — see the home page for current plans.

Frequently asked questions

Can AI really design a working PCB?

For straightforward digital and low-frequency boards, yes: a modern pipeline can select real parts, generate a consistent netlist, place, route, pass DRC and export factory files. Performance-critical work (high-speed, RF, mains power) still needs an engineer setting the constraints and reviewing the result.

Do I need to review an AI-generated board before manufacturing it?

Yes. Read the schematic against your own requirements, check the BOM ratings line by line, open the Gerbers in a viewer, and order a prototype before a production run. BuildPCB is in beta and explicitly recommends professional review for complex boards.

What files does AI PCB design software produce, and will my fab accept them?

A complete package is Gerbers, an Excellon drill file, a bill of materials, a pick-and-place (CPL) file and a 3D model. Those are industry-standard formats that any PCB manufacturer accepts; assembly houses additionally need the BOM and CPL to match your part numbers and rotations.

Why does the component catalog matter so much?

Because a design specifying parts you cannot buy is worthless. Selecting from a live catalog of in-stock components with real manufacturer part numbers means the BOM can actually be quoted, ordered and assembled instead of needing a redesign.

Can an autorouter replace a layout engineer?

Not entirely. Autorouters are very good at connecting nets without violating clearance rules, but they do not model return current, controlled impedance, current-carrying capacity or analog sensitivity. Those have to be expressed as constraints by someone who understands the circuit.